1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to a semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other.
2. Description of the Related Art
In order to make a data transmission speed between a DRAM (Dynamic Random Access Memory) and a logic circuit faster, a logic in memory is used in which the DRAM and the logic circuit are integrated on the same semiconductor chip.
There may be a case that a burn-in is performed on this logic in memory, in order to improve the reliability, similarly to other semiconductor integrated circuits. When the burn-in is performed on the logic in memory, a power supply voltage higher than a sent power supply voltage in a normal operation is sent to the logic in memory, and the operation is carried out in atmosphere at a high temperature. Thus, the deterioration at a defective portion is accelerated to thereby bring about a potential defect in a short time.
When the burn-in is performed on the logic in memory, the DRAM and the logic circuit need to receive the power supply voltages different from each other. This is because the DRAM and the logic circuit have the structures of the semiconductor elements included in them and the manufacturing processes that are different from each other. For example, the thicknesses of gate oxide films of MOS (Metal Oxide Semiconductor) transistors included in the DRAM and the logic circuit are typically different from each other. Thus, it is necessary to perform the burn-in while sending the different power supply voltages to the DRAM and the logic circuit, in order to obtain the fault lives at the same level between the DRAM and the logic circuit. At this time, a power supply voltage higher than that of the logic circuit is typically sent to the DRAM.
At this time, if the DRAM to which the high power supply voltage is sent outputs a signal to the logic circuit to which the low power supply voltage is sent, there may be the fear of a break of a semiconductor element included in the logic circuit. For example, let us consider the DRAM mixture semiconductor integrated circuit, in which a DRAM having a gate oxide film having a film thickness of 9 nm and a logic circuit having a gate oxide film having a film thickness of 6 nm are mixed. It is necessary to send a power supply voltage of 4.5 V to the DRAM at the operation of the burn-in. On the other hand, a power supply voltage of 3.5 V is sent to the logic circuit at the operation of the burn-in. The DRAM to which the power supply voltage of 4.5 V is sent outputs a signal having an amplitude of 4.5 V to the logic circuit. However, the maximum rated voltage of the logic circuit having the gate oxide film having the film thickness of 6 nm is 4.0 V. Thus, there may be the fear the break of this logic circuit when the signal having the amplitude of 4.5 V outputted by the DRAM is inputted.
It is necessary to protect the logic circuit from being damaged, when the DRAM to which the high power supply voltage is sent outputs the signal having the same amplitude as the high power supply voltage, to the logic circuit to which the low power supply voltage is sent, at the operation of the burn-in.
The above-mentioned situation similarly occurs in a semiconductor integrated circuit in which two macros to which different power supply voltages are sent are placed on a single chip. When the semiconductor integrated circuit containing the two macros having the different operational voltages is operated, it is desirable to protect the break of the semiconductor element included in the macro having the lower operational voltage, by sending a signal having a high voltage from the macro having the higher operational voltage to the macro having the lower operational voltage.
By the way, the related technique is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 10-247397). FIG. 1 shows the configuration of the known semiconductor integrated circuit disclosed thereby. A known semiconductor integrated circuit 101 is provided with a memory mat 102, a low decoder 103, a low driver 104, a column decoder 105, a column driver 106, a sense amplifier 107, a low address buffer 108, a column address buffer 109, a data input buffer 110, a data output buffer 111, an input output control circuit 112, an oscillator 113, a booster power supply circuit 114, a level sensor 115 and a control circuit 116.
The known semiconductor integrated circuit 101 stops sending a booster power supply voltage Vpp from the booster power supply circuit 114 when a burn-in test is carried out, and thereby protects the normal circuit elements included in the low decoder 103 and the like from being damaged. If the burn-in test is not done, the booster power supply voltage Vpp is sent from the booster power supply circuit 114 to the low decoder 103. On the other hand, if the burn-in test is done, a power supply voltage is sent to the low decoder 103 from an external portion of the semiconductor integrated circuit 101, and the booster power supply voltage Vpp is not sent from the booster power supply circuit 114. Thus, it is possible to protect the break of the normal circuit elements, when an excessively high voltage is sent to the low decoder 103.
In the logic in memory in which the logic circuit and the DRAM that can be operated although their operational voltages are different from each other are mixed, there may be further a case of an occurrence of an erroneous operation, depending on a timing when the power supply voltages are sent to the DRAM and the logic circuit, respectively, when the power supply is turned on.
This is because the operation of the DRAM is unstable until the power supply voltage sent to the DRAM reaches a certain degree of a voltage, after the power supply is turned on. Thus, this unstable operation may cause a data inputted to the logic circuit from the DRAM to be a data in which an input to the logic circuit is not assumed. The input of such a data to the logic circuit may result in the occurrence of the erroneous operation in the logic circuit.
Moreover, although the power supply voltage sent to the logic circuit does not reach a certain degree of a voltage, if the DRAM starts its operation and outputs a signal to the logic circuit, an improper voltage may be applied to the semiconductor element included in the logic circuit, and a latch-up state may be induced.
It is desirable to protect such an erroneous operation from being brought about when the power supply is turned on.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to protect the break of the semiconductor element included in the macro having the lower operational voltage, by outputting a signal from the macro having the higher operational voltage to the macro having the lower operational voltage, when the semiconductor integrated circuit containing the two macros having the different operational voltages is operated.
Another object of the present invention is to protect the break of the semiconductor element included in the macro having the lower operational voltage, by outputting a signal to the macro on which the burn-in is performed while the lower power supply voltage is sent, from the macro on which the burn-in is performed while the higher power supply voltage is sent, in the semiconductor integrated circuit including the two macros on which the burn-in is performed while the different power supply voltages are sent.
Still another object of the present invention is to protect the break of the semiconductor element included in the logic macro, by outputting a signal to the logic macro on which the burn-in is performed while the lower power supply voltage is sent, from the DRAM macro on which the burn-in is performed while the higher power supply voltage is sent, in the DRAM mixture semiconductor integrated circuit in which the DRAM macro and the logic macro are mixed.
Still another object of the present invention is to protect the erroneous operation of the semiconductor integrated circuit when a power supply to the semiconductor integrated circuit including the two macros is started.
In order to achieve an aspect of the present invention, a semiconductor integrated circuit, includes: a first macro outputting a data signal; and a second macro inputting the data signal, and wherein the first macro fixes the data signal at a non-high level state that is not a high level in response to a control signal.
In this case, the non-high level state is a low level.
Also in this case, when a burn-in is performed on the semiconductor integrated circuit, the control signal indicates that the data signal is fixed at the non-high level state.
Further in this case, when a first power supply voltage supplied to the first macro is higher than a maximum rated voltage of the second macro, the control signal indicates that the data signal is fixed at the non-high level state.
In this case, the semiconductor integrated circuit, further includes: a first POR (Power On Reset) circuit monitoring a first power supply voltage supplied to the first macro and generating the control signal in response to the first power supply voltage, and wherein when the first power supply voltage is lower than a predetermined standard first voltage, the first POR circuit generates the control signal indicating that the data signal is fixed at the non-high level state.
Also in this case, the semiconductor integrated circuit, further includes: a second POR (Power On Reset) circuit monitoring a second power supply voltage supplied to the second macro and generating the control signal in response to the second power supply voltage, and wherein when the second power supply voltage is lower than a predetermined second standard voltage, the second POR circuit generates the control signal indicating that the data signal is fixed at the non-high level state.
Further in this case, the semiconductor integrated circuit, further includes: a third POR (Power On Reset) circuit monitoring a first power supply voltage supplied to the first macro and a second power supply voltage supplied to the second macro and generating the control signal in response to the first and second power supply voltages, and wherein when the first power supply voltage is lower than a predetermined first standard voltage, or the second power supply voltage is lower than a predetermined second standard voltage, the third POR circuit generates the control signal indicating that the data signal is fixed at the non-high level state.
In order to achieve another aspect of the present invention, a semiconductor integrated circuit, includes: a first macro having an output buffer outputting a data signal; and a second macro inputting the data signal, wherein a second power supply voltage is supplied to the second macro, and wherein the second power supply voltage is supplied to the output buffer, and wherein the output buffer outputs the data signal such that an amplitude of the data signal is substantially equal to that of the second power supply voltage.
In this case, a first power supply voltage higher than the second power supply voltage is supplied to a portion other than the output buffer of the first macro.
In order to achieve still another aspect of the present invention, a semiconductor integrated circuit, includes: a first macro outputting a data signal; and a second macro inputting the data signal, and wherein the second macro includes: an input buffer inputting the data signal; a logic circuit inputting an input data signal, wherein the input buffer outputs the input data signal in correspondence with the data signal, and wherein the input buffer includes a first MOS transistor, and wherein the logic circuit includes a second MOS transistor, and wherein a first gate oxide film included in the first MOS transistor is thicker than a second gate oxide film included in the second MOS film.
In this case, a first power supply voltage supplied to the first macro is higher than a second power supply voltage supplied to the second macro.
Also in this case, the first macro includes a third MOS transistor having a third gate oxide film, and wherein the second gate oxide film has a thickness substantially equal to that of the third gate oxide film.
In order to achieve still another aspect of the present invention, a semiconductor integrated circuit, includes: a first macro outputting an output data signal; a level shifter adjusting an amplitude of the output data signal in response to a control signal indicating whether or not a burn-in is performed on the semiconductor integrated circuit to generate an input data signal; and a second macro inputting the input data signal.
In this case, when the burn-in is performed on the semiconductor integrated circuit, the level shifter generates the input data signal such that amplitude of the input data signal is substantially equal to that of a second power supply voltage supplied to the second macro.
Also in this case, wherein a first power supply voltage supplied to the first macro is higher than a second power supply voltage supplied to the second macro.
In order to achieve yet still another aspect of the present invention, an operating method of a semiconductor integrated circuit, includes: (a) inputting a control signal indicating whether or not a burn-in is performed on a semiconductor integrated circuit; and (b) outputting a data signal, and wherein the (b) includes (c) fixing the data signal at non-high level state that is not a high level in response to the control signal when the burn-in is performed on the semiconductor integrated circuit.
In order to achieve another aspect of the present invention, an operating method of a semiconductor integrated circuit, includes: (d) supplying a first power supply voltage to a first macro; and (e) outputting a data signal from the first macro to a second macro, and wherein the (e) includes (f) fixing the data signal at a non-high level state that is not a high level when the first power supply voltage is higher than a maximum rated voltage of the second macro.
In order to achieve still another aspect of the present invention, an operating method of a semiconductor integrated circuit, includes: (g) supplying a power supply voltage; and (h) outputting a data signal, and wherein the (h) includes (i) fixing the data signal at a non-high level than is not a high level when the power supply voltage is lower than a predetermined standard voltage.
In order to achieve yet still another aspect of the present invention, an operating method of a semiconductor integrated circuit, includes: (j) supplying a first power supply voltage to a portion other than an output buffer of a first macro including the output buffer; (k) supplying a second power supply voltage to a second macro and the output buffer; and (l) outputting a data signal of which an amplitude is substantially equal to that of the second power supply voltage from the output buffer to the second macro.
In order to achieve another aspect of the present invention, an operating method of a semiconductor integrated circuit, includes: (m) outputting an output data signal; (n) inputting a control signal indicating whether or not a burn-in is performed on a semiconductor integrated circuit; and (o) adjusting an amplitude of the output data signal in response to the control signal to generate an input data signal.